Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK データシート
製品コード
AT91SAM9N12-EK
508
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
32.8.17 DMAC Channel x [x = 0..7] Control B Register
Name:
DMAC_CTRLBx [x = 0..7]
Addresses:
0xFFFFEC4C [0], 0xFFFFEC74 [1], 0xFFFFEC9C [2], 0xFFFFECC4 [3], 0xFFFFECEC [4], 0xFFFFED14 [5],
0xFFFFED3C [6], 0xFFFFED64 [7]
0xFFFFED3C [6], 0xFFFFED64 [7]
Access:
Read-write
Reset: 0x00000000
This register can only be written if the WPEN bit is cleared in
• SIF: Source Interface Selection Field
• DIF: Destination Interface Selection Field
• SRC_PIP: Source Picture-in-Picture Mode
0 (DISABLE): Picture-in-Picture mode is disabled. The source data area is contiguous.
1 (ENABLE): Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the
address is automatically incremented by a user defined amount.
address is automatically incremented by a user defined amount.
• DST_PIP: Destination Picture-in-Picture Mode
0 (DISABLE): Picture-in-Picture mode is disabled. The Destination data area is contiguous.
1 (ENABLE): Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the
address is automatically incremented by a user-defined amount.
address is automatically incremented by a user-defined amount.
• SRC_DSCR: Source Address Descriptor
0 (FETCH_FROM_MEM): Source address is updated when the descriptor is fetched from the memory.
1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the source.
31
30
29
28
27
26
25
24
AUTO
IEN
DST_INCR
–
–
SRC_INCR
23
22
21
20
19
18
17
16
–
FC
DST_DSCR
–
–
–
SRC_DSCR
15
14
13
12
11
10
9
8
–
–
–
DST_PIP
–
–
–
SRC_PIP
7
6
5
4
3
2
1
0
–
–
DIF
–
–
SIF
Value
Name
Description
00
AHB_IF0
The source transfer is done via AHB_Lite Interface 0 (first DMA Master Interface)
01
AHB_IF1
The source transfer is done via AHB_Lite Interface 1 (second DMA Master Interface)
Value
Name
Description
00
AHB_IF0
The destination transfer is done via AHB_Lite Interface 0 (first DMA Master Interface)
01
AHB_IF1
The destination transfer is done via AHB_Lite Interface 1 (second DMA Master Interface)