Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK データシート
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製品コード
AT91SAM9X25-EK
1004
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
44.9.2 SSC Clock Mode Register
Name:
SSC_CMR
Address:
0xF0010004
Access:
Read-write
This register can only be written if the WPEN bit is cleared in
.
• DIV: Clock Divider
0 = The Clock Divider is not active.
Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2.
The minimum bit rate is MCK/2 x 4095 = MCK/8190.
The minimum bit rate is MCK/2 x 4095 = MCK/8190.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
DIV
7
6
5
4
3
2
1
0
DIV