Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK データシート
製品コード
AT91SAM9X25-EK
312
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
25.7.1 Bus Matrix Master Configuration Registers
Name:
MATRIX_MCFG0...MATRIX_MCFG11
Address:
0xFFFFDE00
Address:
0xFFFFDE04
Address:
0xFFFFDE08
Address:
0xFFFFDE0C
Address:
0xFFFFDE10
Address:
0xFFFFDE14
Address:
0xFFFFDE18
Address:
0xFFFFDE1C
Address:
0xFFFFDE20
Address:
0xFFFFDE28
Address:
0xFFFFDE2C
Access:
Read/Write
This register can only be written if the WPEN bit is cleared in the
.
• ULBT: Undefined Length Burst Type
0: Unlimited Length Burst
No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle
Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next
AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.
Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next
AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.
1: Single Access
The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst.
2: 4-beat Burst
The undefined length burst is split into 4-beat bursts, allowing re-arbitration at each 4-beat burst end.
3: 8-beat Burst
The undefined length burst is split into 8-beat bursts, allowing re-arbitration at each 8-beat burst end.
4: 16-beat Burst
The undefined length burst is split into 16-beat bursts, allowing re-arbitration at each 16-beat burst end.
5: 32-beat Burst
The undefined length burst is split into 32-beat bursts, allowing re-arbitration at each 32-beat burst end.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
ULBT