Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK データシート
製品コード
AT91SAM9X25-EK
334
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
26.5.4.2 16-bit LPDDR on EBI
Hardware Configuration
Software Configuration
The following configuration has to be performed:
Assign EBI_CS1 to the DDR2 controller by setting the bit EBI_CS1A bit in the EBI Chip Select Assignment
Register (CCFG_EBICSA) in the Bus Matrix.
Register (CCFG_EBICSA) in the Bus Matrix.
Initialize the DDR2 Controller depending on the LP-DDR device and system bus frequency.
The LP-DDR initialization sequence is described in the section “Low-power DDR1-SDRAM Initialization” in “DDR/SDR
SDRAM Controller (DDRSDRC)”.
SDRAM Controller (DDRSDRC)”.
In this case VDDNF can be different from VDDIOM. NAND Flash device can be 3.3V or 1.8V and wired on D16–D31 data
bus. NFD0_ON_D16 is to be set to 1.
bus. NFD0_ON_D16 is to be set to 1.