Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK データシート

製品コード

AT91SAM9X25-EK

474

SAM9X25 [DATASHEET]

11054E–ATARM–10-Mar-2014

31.2.1 DMA Controller 0



Two Masters



Embeds 8 channels



64-byte FIFO for channel 0, 16-byte FIFO for Channel 1 to 7



Features:



Linked List support with Status Write Back operation at End of Transfer



Word, HalfWord, Byte transfer support.



Memory to memory transfer



Peripheral to memory



Memory to peripheral

The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the
peripherals below. The hardware interface numbers are also given in

Table 31-1

Table 31-1. DMA Channel Definition

Instance name

T/R

DMA Channel HW

Interface Number

HSMCI0

RX/TX

SPI0

USART0

USART1

TWI0

TWI2

UART0

SSC