Atmel SAM4S-EK2 Atmel ATSAM4S-EK2 ATSAM4S-EK2 データシート
製品コード
ATSAM4S-EK2
877
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.6.5.5 Changing the Comparison Value and the Comparison Configuration
It is possible to change the comparison values and the comparison configurations while the channel 0 is enabled (see
).
(PWM_CMPVUPDx and PWM_CMPMUPDx) to change respectively the
comparison values and the comparison configurations while the channel 0 is still enabled. These registers hold the new
values until the end of the comparison update period (when CUPRCNT is equal to CUPR in
values until the end of the comparison update period (when CUPRCNT is equal to CUPR in
(PWM_CMPMx) and the end of the current PWM period, then update the values for the next period.
CAUTION: to be taken into account, the write of the register PWM_CMPVUPDx must be followed by a write of the
register PWM_CMPMUPDx.
register PWM_CMPMUPDx.
Note:
If the update registers PWM_CMPVUPDx and PWM_CMPMUPDx are written several times between two
updates, only the last written value are taken into account.
updates, only the last written value are taken into account.
Figure 38-19.Synchronized Update of Comparison Values and Configurations
38.6.5.6 Interrupts
Depending on the interrupt mask in the PWM_IMR1 and PWM_IMR2 registers, an interrupt can be generated at the end
of the corresponding channel period (CHIDx in the PWM_ISR1 register), after a fault event (FCHIDx in the PWM_ISR1
register), after a comparison match (CMPMx in the PWM_ISR2 register), after a comparison update (CMPUx in the
PWM_ISR2 register) or according to the transfer mode of the synchronous channels (WRDY, ENDTX, TXBUFE and
UNRE in the PWM_ISR2 register).
of the corresponding channel period (CHIDx in the PWM_ISR1 register), after a fault event (FCHIDx in the PWM_ISR1
register), after a comparison match (CMPMx in the PWM_ISR2 register), after a comparison update (CMPUx in the
PWM_ISR2 register) or according to the transfer mode of the synchronous channels (WRDY, ENDTX, TXBUFE and
UNRE in the PWM_ISR2 register).
If the interrupt is generated by the flags CHIDx or FCHIDx, the interrupt remains active until a read operation in the
PWM_ISR1 register occurs.
PWM_ISR1 register occurs.
If the interrupt is generated by the flags WRDY or UNRE or CMPMx or CMPUx, the interrupt remains active until a read
operation in the PWM_ISR2 register occurs.
operation in the PWM_ISR2 register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER1 and PWM_IER2 registers. A channel
interrupt is disabled by setting the corresponding bit in the PWM_IDR1 and PWM_IDR2 registers.
interrupt is disabled by setting the corresponding bit in the PWM_IDR1 and PWM_IDR2 registers.
PWM_CMPVUPDx Value
Comparison Value
for comparison x
User s Writing
PWM_CMPVx
End of channel0 PWM period and
end of Comparison Update Period
end of Comparison Update Period
PWM_CMPMUPDx Value
Comparison configuration
for comparison x
PWM_CMPMx
User s Writing
End of channel0 PWM period and
end of Comparison Update Period and
and PWM_CMPMx written
end of Comparison Update Period and
and PWM_CMPMx written