Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート
製品コード
AT91SAM9M10-G45-EK
1012
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
43.7.3.5
AC97 Input Frame
The AC97 Controller receives a thirteen slot frame on the AC-Link sent by the AC97 Codec. The first slot (tag slot
or slot 0) flags the validity of the entire frame and the validity of each slot; whether a slot carries valid data or not.
Slots 1 and 2 are used if the application requires status informations from AC97 Codec. Slots [3:12] are used
according to AC97 Controller Output Channel Assignment Register (AC97C_ICA) content. The AC97 Controller
will not receive any data from any slot if AC97C_ICA is not assigned to a channel in input.
or slot 0) flags the validity of the entire frame and the validity of each slot; whether a slot carries valid data or not.
Slots 1 and 2 are used if the application requires status informations from AC97 Codec. Slots [3:12] are used
according to AC97 Controller Output Channel Assignment Register (AC97C_ICA) content. The AC97 Controller
will not receive any data from any slot if AC97C_ICA is not assigned to a channel in input.
43.7.3.6
Configuring and Using Interrupts
Instead of polling flags in AC97 Controller Global Status Register (AC97C_SR) and in AC97 Controller Channel x
Status Register (AC97C_CxSR), the application can wait for an interrupt notice. The following steps show how to
configure and use interrupts correctly:
Status Register (AC97C_CxSR), the application can wait for an interrupt notice. The following steps show how to
configure and use interrupts correctly:
• Set the interruptible flag in AC97 Controller Channel x Mode Register (AC97C_CxMR).
• Set the interruptible event and channel event in AC97 Controller Interrupt Enable Register (AC97C_IER).
The interrupt handler must read both AC97 Controller Global Status Register (AC97C_SR) and AC97 Controller
Interrupt Mask Register (AC97C_IMR) and AND them to get the real interrupt source. Furthermore, to get which
event was activated, the interrupt handler has to read AC97 Controller Channel x Status Register (AC97C_CxSR),
x being the channel whose event triggers the interrupt.
Interrupt Mask Register (AC97C_IMR) and AND them to get the real interrupt source. Furthermore, to get which
event was activated, the interrupt handler has to read AC97 Controller Channel x Status Register (AC97C_CxSR),
x being the channel whose event triggers the interrupt.
The application can disable event interrupts by writing in AC97 Controller Interrupt Disable Register (AC97C_IDR).
The AC97 Controller Interrupt Mask Register (AC97C_IMR) shows which event can trigger an interrupt and which
one cannot.
The AC97 Controller Interrupt Mask Register (AC97C_IMR) shows which event can trigger an interrupt and which
one cannot.
43.7.3.7
Endianness
Endianness can be managed automatically for each channel, except for the Codec channel, by writing to Channel
Endianness Mode (CEM) in AC97C_CxMR. This enables transferring data on AC-link in Big Endian format without
any additional operation.
Endianness Mode (CEM) in AC97C_CxMR. This enables transferring data on AC-link in Big Endian format without
any additional operation.
43.7.3.8
To Transmit a Word Stored in Big Endian Format on AC-link
Word to be written in AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR) (as it is stored in
memory or microprocessor register).
memory or microprocessor register).
Word stored in Channel x Transmit Holding Register (AC97C_CxTHR) (data to transmit)
.
Data transmitted on appropriate slot: data[19:0] = {Byte2[3:0], Byte1[7:0], Byte0[7:0]}.
43.7.3.9
To Transmit A Halfword Stored in Big Indian Format on AC-link
Halfword to be written in AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR).
Halfword stored in AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR) (data to transmit).
Data emitted on related slot: data[19:0] = {0x0, Byte1[7:0], Byte0[7:0]}.
31
24
23
16
15
8
7
0
Byte0[7:0]
Byte1[7:0]
Byte2[7:0]
Byte3[7:0]
31
24
23
20
19
16
15
8
7
0
–
–
Byte2[3:0]
Byte1[7:0]
Byte0[7:0]
31
24
23
16
15
8
7
0
–
–
Byte0[7:0]
Byte1[7:0]
31
24
23
16
15
8
7
0
–
–
Byte1[7:0]
Byte0[7:0]