Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート
製品コード
AT91SAM9M10-G45-EK
1113
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
46.4
Product Dependencies
46.4.1
Power Management
The Video Decoder requires a peripheral clock. The user has to enable UHP peripheral clock, bit (1 <<
AT91C_ID_VDEC) in PMC_PCER register.
AT91C_ID_VDEC) in PMC_PCER register.
Software can reset the hardware synchronically by writing separate decoder and post-processor enable bits to
zero. These enable bits are located in the memory-mapped registers and they can be used for terminating or
restarting the decoding or post-processing at any time.
zero. These enable bits are located in the memory-mapped registers and they can be used for terminating or
restarting the decoding or post-processing at any time.
46.4.2
Interrupt
The Video Decoder has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling Video
Decoder interrupts requires programming the AIC before.
Table 46-7.
Peripheral IDs
Instance
ID
VDEC
30