Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG).

The Bus Matrix contains specific logic to break long accesses, such as back to back undefined length bursts or
very long bursts on a very slow slave (e.g., an external low speed memory). At each arbitration time a counter is
loaded with the value previously written in the SLOT_CYCLE field of the related Slave Configuration Register
(MATRIX_SCFG) and decreased at each clock cycle. When the counter elapses, the arbiter has the ability to re-
arbitrate at the end of the current AHB bus access cycle.

Unless some master has a very tight access latency constraint which could lead to data overflow or underflow due
to a badly undersized internal fifo with respect to its throughput, the Slot Cycle Limit should be disabled
(SLOT_CYCLE = 0) or let to its default maximum value in order not to inefficiently break long bursts performed by
some ATMEL masters.

However, the Slot Cycle Limit should not be disabled in the very particular case of a master capable of accessing
the slave by performing back to back undefined length bursts shorter than the number of ULBT beats with no Idle
cycle in between, since in this case the arbitration could be frozen all along the bursts sequence.

In most cases this feature is not needed and should be disabled for power saving.

Warning: This feature cannot prevent any slave from locking its access indefinitely.

The bus Matrix arbitration scheme is organized in priority pools.

Round-Robin priority is used inside the highest and lowest priority pools, whereas fix level priority is used between
priority pools and inside the intermediate priority pools.

For each slave, each master x is assigned to one of the slave priority pools through the Priority Registers for
Slaves (MxPR fields of MATRIX_PRAS and MATRIX_PRBS). When evaluating masters requests, this pro-
grammed priority level always takes precedence.

After reset, all the masters are belonging to the lowest priority pool (MxPR = 0) and so are granted bus access in a
true Round-Robin fashion.

The highest priority pool must be specifically reserved for masters requiring very low access latency. If more than
one master belong to this pool, these will be granted bus access in a biased Round-Robin fashion which allow tight
and deterministic maximum access latency from AHB bus request. In fact, at worst, any currently high priority mas-
ter request will be granted after the current bus master access is ended and the other high priority pool masters, if
any, have been granted once each.

The lowest priority pool shares the remaining bus bandwidth between AHB Masters.

Intermediate priority pools allow fine priority tuning. Typically, a moderately latency critical master or a bandwidth
only critical master will use such a priority level. The higher the priority level (MxPR value), the higher the master
priority.

All combination of MxPR values are allowed for all masters and slaves. For example some masters might be
assigned to the highest priority pool (round-robin) and the remaining masters to the lowest priority pool (round-
robin), with no master for intermediate fix priority levels.

If more than one master is requesting the slave bus, whatever are the respective masters priorities, no master will
be granted the slave bus for two consecutive runs. A master can only get back to back grants as long as it is the
only requesting master.