Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The pins used for interfacing the DDR2 memory are not multiplexed with the PIO lines.

The following hardware configuration is given for illustration only. The user should refer to the memory manufac-
turer web site to check current device availability.

DDR2 I/O Lines Description 

DDR_D0 - DDR_D15

Data Bus

I/O

DDR_A0 - DDR_A13

Address Bus

Output

DDR_DQM0 - DDR_DQM1

Data Mask

Output

DDR_DQS0 - DDR_DQS1

Data Strobe

Output

DDR_VREF

Reference Voltage for DDR2 operations, typically 0.9V

Input

DDR_CS

Chip Select

Output

Low

DDR_CLK - DDR_CLK#

DDR2 Differential Clock

Output

DDR_CKE

Clock enable

Output

High

DDR_RAS

Row signal

Output

Low

DDR_CAS

Column signal

Output

Low

DDR_WE

Write enable

Output

Low

DDR_BA0 - DDR_BA1

Bank Select

Output