Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート
製品コード
AT91SAM9M10-G45-EK
160
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
20.2.5
Application Example
20.2.5.1
Hardware Interface
details the connections to be applied between the EBI pins and the external devices for
each Memory Controller.
Notes:
1. NWR1 enables upper byte writes. NWR0 enables lower byte writes.
1. NWRx enables corresponding byte x writes. (x = 0,1,2 or 3)
2. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word.
3. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word.
2. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word.
3. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word.
Table 20-4.
EBI Pins and External Static Devices Connections
Signals:
EBI_
Pins of the Interfaced Device
8-bit Static
Device
2 x 8-bit
Static
Devices
16-bit Static
Device
4 x 8-bit
Static
Devices
2 x 16-bit
Static
Devices
32-bit Static
Device
Controller
SMC
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D8 - D15
–
D8 - D15
D8 - D15
D8 - D15
D8 - 15
D8 - 15
D16 - D23
–
–
–
D16 - D23
D16 - D23
D16 - D23
D24 - D31
–
–
–
D24 - D31
D24 - D31
D24 - D31
A0/NBS0
A0
–
NLB
–
NLB
(3)
BE0
A1/NWR2/NBS2
A1
A0
A0
WE
(2)
NLB
(4)
BE2
A2 - A22
A[2:22]
A[1:21]
A[1:21]
A[0:20]
A[0:20]
A[0:20]
A23 - A25
(5)
A[23:25]
A[22:24]
A[22:24]
A[21:23]
A[21:23]
A[21:23]
NCS0
CS
CS
CS
CS
CS
CS
NCS1/DDRSDCS
CS
CS
CS
CS
CS
CS
NCS2
CS
CS
CS
CS
CS
CS
NCS3/NANDCS
CS
CS
CS
CS
CS
CS
NCS4/CFCS0
CS
CS
CS
CS
CS
CS
NCS5/CFCS1
CS
CS
CS
CS
CS
CS
NRD/CFOE
OE
OE
OE
OE
OE
OE
NWR0/NWE
WE
WE
(1)
WE
WE
(2)
WE
WE
NWR1/NBS1
–
WE
(1)
NUB
WE
(2)
NUB
(3)
BE1
NWR3/NBS3
–
–
–
WE
(2)
NUB
(4)
BE3