Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer
must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O
lines of the External Bus Interface are not used by the application, they can be used for other purposes by the PIO
Controller.

The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the external memories or
peripheral devices. It controls the waveforms and the parameters of the external address, data and control buses
and is composed of the following elements:

• the Static Memory Controller (SMC)

• the DDR2/SDRAM Controller (DDR2SDRAMC)

• the ECC Controller (ECC)

• a chip select assignment feature that assigns an AHB address space to the external devices

• a multiplex controller circuit that shares the pins between the different Memory Controllers

• programmable CompactFlash support logic

• programmable NAND Flash support logic

The EBI offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits
and the control signals through a multiplex logic operating in function of the memory area requests.

Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines
at a stable state while no external access is being performed. Multiplexing is also designed to respect the data float
times defined in the Memory Controllers. Furthermore, refresh cycles of the DDR2 and SDRAM are executed inde-
pendently by the DDR2SDRAM Controller without delaying the other external Memory Controller accesses.

The EBI_CSA registers in the Chip Configuration User Interface permit enabling of on-chip pull-up resistors on the
data bus lines not multiplexed with the PIO Controller lines. The pull-up resistors are enabled after reset. Setting
the EBIx_DBPUC bit disables the pull-up resistors on the D0 to D15 lines. Enabling the pull-up resistor on the D16-
D31 lines can be performed by programming the appropriate PIO controller.

For information on the Static Memory Controller, refer to the Static Memory Controller section.

For information on the DDR2SDRAM Controller, refer to the DDR2SDRAMC section.

For information on the ECC Controller, refer to the ECC section.

The External Bus Interface 0 integrates circuitry that interfaces to CompactFlash devices.

The CompactFlash logic is driven by the Static Memory Controller (SMC) on the NCS4 and/or NCS5 address
space. Programming the EBI_CS4A and/or EBI_CS5A bit of the EBI_CSA Register in the Chip Configuration User
Interface to the appropriate value enables this logic.

 

(For details on this register, refer to the Chip Configuration