Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート

製品コード

AT91SAM9M10-G45-EK

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

• Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block anywhere in the ARM926

data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master
and by the AHB Masters through the AHB bus.

• Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap Command is

performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB
Masters. After Remap, this SRAM block also becomes accessible through the AHB bus at address 0x0 by the
ARM926 Instruction and the ARM926 Data Masters.

Within the 64 Kbyte SRAM size available, the amount of memory assigned to each block is software programma-
ble according to

Table 6-1

6.2.3

Internal ROM

The SAM9M10 embeds an Internal ROM, which contains the boot ROM and SAM-BA

program.

At any time, the ROM is mapped at address 0x0040 0000. It is also accessible at address 0x0 (BMS =1) after the
reset and before the Remap Command.

6.3

I/O Drive Selection and Delay Control

6.3.1

I/O Drive Selection

The aim of this control is to adapt the signal drive to the frequency. Two bits allow the user to select High or Low
drive for memories data/address/ctrl signals.

• Setting the bit [17], EBI_DRIVE, in the EBI_CSA register of the matrix allows to control the drive of the EBI.

• Setting the bit [18], DDR_DRIVE, in the EBI_CSA register of the matrix allows to control the drive of the DDR.

6.3.2

Delay Control

To avoid the simultaneous switching of all the I/Os, a delay can be inserted on the different EBI, DDR2 and PIO
lines.

The control of these delays is the following:

• DDRSDRC

DDR_D[15:0]

controlled by 2 registers, DELAY1 and DELAY2, located in the DDRSDRC user interface

– DDR_D[0] <=> DELAY1[3:0],

– DDR_D[1] <=> DELAY1[7:4],...

– DDR_D[6] <=> DELAY1[27:24],

– DDR_D[7] <=> DELAY1[31:28]

– DDR_D[8] <=> DELAY2[3:0],

– DDR_D[9] <=> DELAY2[7:4],...,

– DDR_D[14] <=> DELAY2[27:24],

Table 6-1.

ITCM and DTCM Memory Configuration

SRAM A ITCM size (KBytes)

seen at 0x100000 through AHB

SRAM B DTCM size (KBytes)

seen at 0x200000 through AHB

SRAM C (KBytes)

seen at 0x300000 through AHB