Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The initialization sequence is generated by software. The DDR2-SDRAM devices are initialized by the following
sequence:

1.

2.

Program the features of DDR2-SDRAM device into the Timing Register (asynchronous timing (trc, tras, 
etc.)), and into the Configuration Register (number of columns, rows, cas latency and output drive 
strength) (see 

3.

An NOP command is issued to the DDR2-SDRAM. Program the NOP command into the Mode Register, 
the application must set Mode to 1 in the Mode Register (see 

write access to any DDR2-SDRAM address to acknowledge this command. Now clocks which drive 
DDR2-SDRAM device are enabled.

A minimum pause of 200 μs is provided to precede any signal toggle.

4.

An NOP command is issued to the DDR2-SDRAM. Program the NOP command into the Mode Register, 
the application must set Mode to 1 in the Mode Register (see 

write access to any DDR2-SDRAM address to acknowledge this command. Now CKE is driven high.

5.

An all banks precharge command is issued to the DDR2-SDRAM. Program all banks precharge command 
into the Mode Register, the application must set Mode to 2 in the Mode Register (See 

6.

An Extended Mode Register set (EMRS2) cycle is issued to chose between commercial or high tempera-
ture operations. The application must set Mode to 5 in the Mode Register (see 

) and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address 

must be chosen so that BA[1] is set to 1 and BA[0] is set to 0. For example, with a 16-bit 128 MB DDR2-
SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access should be done at 
the address 0x20800000.

Note:

This address is for example purposes only. The real address is dependent on implementation in the product. 

7.

An Extended Mode Register set (EMRS3) cycle is issued to set the Extended Mode Register to “0”. The 
application must set Mode to 5 in the Mode Register (see 

write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so 
that BA[1] is set to 1 and BA[0] is set to 1. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 
columns, 4 banks) bank address, the DDR2-SDRAM write access should be done at the address 
0x20C00000.

8.

An Extended Mode Register set (EMRS1) cycle is issued to enable DLL. The application must set Mode 
to 5 in the Mode Register (see 

) and perform a write access to the DDR2-

SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 0 and 
BA[0] is set to 1. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank 
address, the DDR2-SDRAM write access should be done at the address 0x20400000.

An additional 200 cycles of clock are required for locking DLL

9.

Program DLL field into the Configuration Register (see 

) to high (Enable DLL 

reset).

10. A Mode Register set (MRS) cycle is issued to reset DLL. The application must set Mode to 3 in the Mode 

edge this command. The write address must be chosen so that BA[1:0] bits are set to 0. For example, with 
a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access 
should be done at the address 0x20000000.

11. An all banks precharge command is issued to the DDR2-SDRAM. Program all banks precharge command 

12. Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode 

Register, the application must set Mode to 4 in the Mode Register (see 

). Per-

forms a write access to any DDR2-SDRAM location twice to acknowledge these commands.