Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート

 253

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

DDRSDRC_RTR

0xFFFFE604 (0), 0xFFFFE404 (1)

Read-write

See 

This register can only be written if the bit WPEN is cleared in 

.

This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a refresh
sequence is initiated. 

SDRAM devices require a refresh of all rows every 64 ms. The value to be loaded depends on the DDRSDRC clock fre-
quency (MCK: Master Clock) and the number of rows in the device.

For example, for an SDRAM with 8192 rows and a 100 MHz Master clock, the value of Refresh Timer Count bit is pro-
grammed: (((64 x 10

-3

)/8192) x100 x10

6

 = 781 or 0x030D.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

–

15

14

13

12

11

10

9

8

–

–

–

–

COUNT

7

6

5

4

3

2

1

0

COUNT