Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート
製品コード
AT91SAM9M10-G45-EK
257
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
22.8.4
DDRSDRC Timing Parameter 0 Register
Name:
DDRSDRC_TPR0
Address:
0xFFFFE60C (0), 0xFFFFE40C (1)
Access:
Read-write
Reset:
See
This register can only be written if the bit WPEN is cleared in
.
• TRAS: Active to Precharge Delay
Reset Value is 5 cycles.
This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of
cycles is between 0 and 15.
cycles is between 0 and 15.
• TRCD: Row to Column Delay
Reset Value is 2 cycles.
This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of
cycles is between 0 and 15.
cycles is between 0 and 15.
• TWR: Write Recovery Delay
Reset value is 2 cycles.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 1 and 15.
• TRC: Row Cycle Delay
Reset value is 7 cycles.
This field defines the delay between an Activate command and Refresh command in number of cycles. Number of cycles is
between 0 and 15
between 0 and 15
• TRP: Row Precharge Delay
Reset Value is 2 cycles.
This field defines the delay between a Precharge Command and another command in number of cycles. Number of cycles
is between 0 and 15.
is between 0 and 15.
• TRRD: Active bankA to Active bankB
Reset value is 2 cycles.
This field defines the delay between an Active command in BankA and an active command in bankB in number of cycles.
Number of cycles is between 1 and 15.
Number of cycles is between 1 and 15.
31
30
29
28
27
26
25
24
TMRD
REDUCE_WRRD
TWTR
23
22
21
20
19
18
17
16
TRRD
TRP
15
14
13
12
11
10
9
8
TRC
TWR
7
6
5
4
3
2
1
0
TRCD
TRAS