Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

• RISC Processor Based on ARM v5TEJ Architecture with Jazelle

®

 technology for Java

®

 acceleration

• Two Instruction Sets

– ARM High-performance 32-bit Instruction Set

– Thumb High Code Density 16-bit Instruction Set

• DSP Instruction Extensions

• 5-Stage Pipeline Architecture:

– Instruction Fetch (F)

– Instruction

 

Decode (D)

– Execute (E)

– Data Memory (M)

– Register Write (W)

• 32-KByte Data Cache, 32-KByte Instruction Cache

– Virtually-addressed 4-way Associative Cache

– Eight words per line

– Write-through and Write-back Operation

– Pseudo-random or Round-robin Replacement

• Write Buffer

– Main Write Buffer with 16-word Data Buffer and 4-address Buffer

– DCache Write-back Buffer with 8-word Entries and a Single Address Entry

– Software Control Drain

• Standard ARM v4 and v5 Memory Management Unit (MMU)

– Access Permission for Sections

– Access Permission for large pages and small pages can be specified separately for each quarter of the 

page 

– 16 embedded domains

• Bus Interface Unit (BIU)

– Arbitrates and Schedules AHB Requests

– Separate Masters for both instruction and data access providing complete Matrix system flexibility

– Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface

– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)

• TCM Interface