Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート

 369

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

Master Mode Flow Diagram

 shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Reg-

ister Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Register) during an 8-bit data transfer in
fixed mode and no Peripheral Data Controller involved.

SPI Enable

CSAAT 

PS 

1

0

0

1

1

NPCS = SPI_TDR(PCS)

NPCS = SPI_MR(PCS)

Delay DLYBS

Serializer = SPI_TDR(TD)

TDRE = 1

Data Transfer

SPI_RDR(RD) = Serializer

RDRF = 1

TDRE 

NPCS = 0xF

Delay DLYBCS

Fixed

 peripheral

Variable 

peripheral

Delay DLYBCT

0

1

CSAAT 

0

TDRE 

1

0

PS 

0

1

SPI_TDR(PCS)

= NPCS 

no

yes

SPI_MR(PCS)

= NPCS 

no

NPCS = 0xF

Delay DLYBCS

NPCS = SPI_TDR(PCS)

NPCS = 0xF

Delay DLYBCS

NPCS = SPI_MR(PCS),

                SPI_TDR(PCS) 

Fixed

 peripheral

Variable 

peripheral

- NPCS defines the current Chip Select
- CSAAT, DLYBS, DLYBCT refer to the fields of the 
  Chip Select Register corresponding to the Current Chip Select
- When NPCS is 0xF, CSAAT is 0.