Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data
for cache line eviction or cleaning of dirty cache lines.

The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer opera-
tions are closely connected as their configuration is set in each section by the page descriptor in the MMU
translation table.

The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. The write buf-
fer is used for all writes to a bufferable region, write-through region and write-back region. It also allows to avoid
stalling the processor when writes to external memory are performed. When a store occurs, data is written to the
write buffer at core speed (high speed). The write buffer then completes the store to external memory at bus speed
(typically slower than the core speed). During this time, the ARM9EJ-S processor can preform other tasks.

DCache and Write Buffer support write-back and write-through memory regions, controlled by C and B bits in each
section and page descriptor within the MMU translation tables.

When a cache write hit occurs, the DCache line is updated. The updated data is then written to the write buffer
which transfers it to external memory.

When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer
which transfers it to external memory.

When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-
to-date with those in the external memory.

When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer
which transfers it to external memory.

The ARM926EJ-S processor features a Tightly-coupled Memory (TCM) interface, which enables separate instruc-
tion and data TCMs (ITCM and DTCM) to be directly reached by the processor. TCMs are used to store real-time
and performance critical code, they also provide a DMA support mechanism. Unlike AHB accesses to external
memories, accesses to TCMs are fast and deterministic and do not incur bus penalties.

The user has the possibility to independently configure each TCM size with values within the following ranges, [0K
Byte, 64K Bytes] for ITCM size and [0K Byte, 64K Bytes] for DTCM size. 

TCMs can be configured by two means: HMATRIX TCM register and TCM region register (register 9) in CP15 and
both steps should be performed. HMATRIX TCM register sets TCM size whereas TCM region register (register 9)
in CP15 maps TCMs and enables them.

The data side of the ARM9EJ-S core is able to access the ITCM. This is necessary to enable code to be loaded
into the ITCM, for SWI and emulated instruction handlers, and for accesses to PC-relative literal pools.

Prior to any enabling step, the user should configure the TCM sizes in HMATRIX TCM register. Then enabling
TCMs is performed by using TCM region register (register 9) in CP15. The user should use the same sizes as
those put in HMATRIX TCM register. For further details and programming tips, please refer to chapter 2.3 in
ARM926EJ-S TRM.