Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート
製品コード
AT91SAM9M10-G45-EK
489
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
31.7.3.9
Parity
The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR).
The PAR field also enables the Multidrop mode, see
The PAR field also enables the Multidrop mode, see
. Even and odd parity bit gener-
ation and error detection are supported.
If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the
character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the
number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is
selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is
even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s
and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity gener-
ator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the
parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0
for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled,
the transmitter does not generate any parity bit and the receiver does not report any parity error.
character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the
number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is
selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is
even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s
and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity gener-
ator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the
parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0
for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled,
the transmitter does not generate any parity bit and the receiver does not report any parity error.
shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the con-
figuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a
parity is even.
parity is even.
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register
(US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1.
(US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1.
Figure 31-22.
Parity Error
Table 31-9.
Parity Bit Examples
Character
Hexa
Binary
Parity Bit
Parity Mode
A
0x41
0100 0001
1
Odd
A
0x41
0100 0001
0
Even
A
0x41
0100 0001
1
Mark
A
0x41
0100 0001
0
Space
A
0x41
0100 0001
None
None
D0
D1
D2
D3
D4
D5
D6
D7
RXD
Start
Bit
Bad
Parity
Bit
Stop
Bit
Baud Rate
Clock
Write
US_CR
PARE
RXRDY
RSTSTA = 1