Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

Master Write with One Byte Internal Address and Multiple Data Bytes

The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-
bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in
this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the
data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data
line during this clock pulse and sets the 

 bit in the status register if the slave does not acknowledge the byte.

If an acknowledge is received, the master is then ready to receive data from the slave. After data has been
received, the master sends an acknowledge condition to notify the slave that the data has been received except for
the last data, after the stop condition. See 

. When the RXRDY bit is set in the status register, a charac-

ter has been received in the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the
TWI_RHR.

When a single data byte read is performed, with or without internal address 

), the START and STOP bits

. When a multiple data byte read is performed, with or without inter-

nal address 

. For Internal

.

Master Read with One Data Byte

A

DATA n

A

S

DADR

W

DATA n+1

A

P

DATA n+2

A

TXCOMP

TXRDY

Write THR (Data n)

Write THR (Data n+1)

Write THR (Data n+2)

Last data sent

STOP command performed

(by writing in the TWI_CR)

TWD

IADR

A

TWCK

A

S

DADR

R

DATA

N

P

TXCOMP

Write START & 

STOP Bit

RXRDY

Read RHR

TWD