Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート

 601

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

Transmitter Clock Management

The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the
RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register).
Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. 

The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output
is configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock out-
puts. Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive
Clock (CKO field) can lead to unpredictable results.

Receiver Clock Management

The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK
or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock
speed allowed on the RK pin is:

– Master Clock divided by 2 if Receiver Frame Synchro is input

TK (pin)

Receiver

Clock

Divider

Clock

CKS

CKO

 Data Transfer

CKI

CKG

Transmitter
Clock

Clock
Output

MUX

Tri_state

Controller

Tri-state

Controller

INV

MUX

RK (pin)

Transmitter

Clock

Divider

Clock

CKS

CKO

Data Transfer

CKI

CKG

Receiver
Clock

Clock
Output

MUX

Tri-state

Controller

Tri-state

Controller

INV

MUX