Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The TSADCC embeds a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The ADC
supports 8-bit or 10-bit resolutions.

The conversion is performed on a full range between 0V and the reference voltage pin TSADVREF. Analog inputs
between these voltages convert to values based on a linear conversion.

The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the bit LOWRES in the
TSADCC Mode Register. See 

. 

By default, after a reset, the resolution is the highest and the DATA field in the 

 are fully used. 

By setting the bit LOWRES, the ADC switches in the lowest resolution and the conversion results can be read in
the eight lowest significant bits of the data registers. The two highest bits of the DATA field in the corresponding
TSADCC_CDR register and of the LDATA field in the TSADCC_LCDR register read 0. 

Moreover, when a PDC channel is connected to the TSADCC, 10-bit resolution sets the transfer request sizes to
16-bit. Setting the bit LOWRES automatically switches to 8-bit data transfers. In this case, the destination buffers
are optimized.

All the conversions for the Touch Screen forces the ADC in 10-bit resolution, regardless of the LOWRES setting.
Further details are given in the section 

.

The TSADCC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-bit digital data
requires Sample and Hold Clock cycles as defined in the field SHTIM of the 

 and 10 ADC

The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/128, if PRESCAL is set to 63 (0x3F). PRES-
CAL must be programmed in order to provide an ADC clock frequency according to the maximum sampling rate
parameter given in the Electrical Characteristics section.

The TSADCC Sleep Mode maximizes power saving by automatically deactivating the Analog-to-Digital Converter
cell when it is not being used for conversions. Sleep Mode is enabled by setting the bit SLEEP in 

The SLEEP of the ADC is automatically managed by the conversion sequencer, which can automatically process
the conversions of all channels at lowest power consumption.

When a trigger occurs, the Analog-to-Digital Converter cell is automatically activated. As the analog cell requires a
start-up time, the logic waits during this time and then starts the conversion on the enabled channels. When all
conversions are complete, the ADC is deactivated until the next trigger. 

The Touch Screen ADC has a minimal Startup Time when it exits the Sleep Mode. As the ADC Clock depends on
the application, the user has to program the field STARTUP in the 

, which defines how

many ADC Clock cycles to wait before performing the first conversion of the sequence. 

The field STARTUP can define a Startup Time between 8 and 1024 ADC Clock cycles by steps of 8.

The user must assure that ADC Startup Time given in the section “Electrical Characteristics” is covered by this wait
time.