Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート

 939

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

At the end of every buffer transfer, an end of buffer interrupt is asserted if:

• the channel buffer interrupt is unmasked, DMAC_EBCIMR.BTC[n] = ‘1’, where n is the channel number.

Note:

The buffer complete interrupt is generated at the completion of the buffer transfer to the destination.

At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if:

• the channel end of chained buffer interrupt is unmasked, DMAC_EBCIMR.CBTC[n] = ‘1’, when n is the channel 

number.

All multi-buffer transfers must end as shown in Row 1 of 

. At the end of every buffer trans-

fer, the DMAC samples the row number, and if the DMAC is in Row 1 state, then the previous buffer transferred
was the last buffer and the DMAC transfer is terminated. 

For rows 9, 10 and 11 of 

, (DMAC_DSCRx = 0 and DMAC_CTRLBx.AUTO is set), multi-

buffer DMAC transfers continue until the automatic mode is disabled by writing a ‘1’ in DMAC_CTRLBx.AUTO bit.
This bit should be programmed to zero in the end of buffer interrupt service routine that services the next-to-last
buffer transfer. This puts the DMAC into Row 1 state.

For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared) the user must setup the last buffer descriptor in mem-
ory such that both LLI.DMAC_CTRLBx.SRC_DSCR and LLI.DMAC_CTRLBx.DST_DSCR are one and
LLI.DMAC_DSCRx is set to 0.