Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK データシート

187

SAM9G25 [DATASHEET]

11032D–ATARM–10-Mar-2014

The USB Device and Host High Speed ports clocks are controlled by the UDPHS and UHPHS bits in PMC_PCER. To 
save power on this peripheral when they are is not used, the user can set these bits in PMC_PCDR. The UDPHS and 
UHPHS bits in PMC_PCR give the activity of these clocks.

The PMC also provides the clocks UHP48M and UHP12M to the USB Host OHCI. The USB Host OHCI clocks are 
controlled by the UHP bit in PMC_SCER. To save power on this peripheral when it is not used, the user can set the UHP 
bit in PMC_SCDR. The UHP bit in PMC_SCSR gives the activity of this clock. The USB host OHCI requires both the 
12/48 MHz signal and the Master Clock. USBDIV field in PMC_USB register is to be programmed to 9 (division by 10) for 
normal operations.

To save more power consumption the user can stop UTMI PLL, in this case USB high-speed operations are not possible. 
Nevertheless, as the USB OHCI Input clock can be selected with USBS bit (PLLA or UTMI PLL) in PMC_USB register, 
OHCI full-speed operation remain possible.

The user must program the USB OHCI Input Clock and the USBDIV divider in PMC_USB register to generate a 48 MHz 
and a 12 MHz signal with an accuracy of 

±

 0.25%.

The Power Management Controller controls the clocks of the DDR memory. 

The DDR clock can be enabled and disabled with DDRCK bit respectively in PMC_SCER and PMC_SDER registers. At 
reset DDR clock is disabled to save power consumption.

In the case MDIV = ‘00’, (PCK = MCK)  and DDRCK clock is not available.

If Input clock is PLLACK/PLLADIV2 the DDR Controller can drive DDR2 and LP-DDR at up to 133 MHz with MDIV = ‘11’.

To save PLLA power consumption, the user can choose UPLLCK an Input clock for the system. In this case the DDR 
Controller can drive LD-DDR at up to 120 MHz.

The Power Management Controller controls the clocks of the Software Modem.

SMDCK is a division of UPLL or PLLA.

The Power Management Controller controls the clocks of each embedded peripheral by means of the Peripheral Clock 
Controller. The user can individually enable and disable the clock on the peripherals and select a division factor from 
MCK. This is done through the Peripheral Control Register (PMC_PCR).

In order to save power consumption, the division factor can be 1, 2, 4 or 8. PMC_PCR is a register that features a 
command and acts like a mailbox. To write the division factor on a particular peripheral, the user needs to write a WRITE 
command, the peripheral ID and the chosen division factor. To read the current division factor on a particular peripheral, 
the user just needs to write the READ command and the peripheral ID.

Code Example to select divider 8 for peripheral 2 and enable its clock: 

write_register(PMC_PCR,0x010031002)

Code Example to read the divider of peripheral 4: 

write_register(PMC_PCR,0x00000004)

read_register(PMC_PCR)

When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically disabled 
after a reset.

In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last 
programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system.