Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK データシート
製品コード
AT91SAM9G25-EK
191
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
22.12 Clock Switching Details
22.12.1 Master Clock Switching Timings
give the worst case timings required for the Master Clock to switch from one selected clock to
another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of
64 clock cycles of the new selected clock has to be added.
64 clock cycles of the new selected clock has to be added.
Notes: 1.
PLL designates either the PLLA or the UPLL Clock.
2.
PLLCOUNT designates either PLLACOUNT or UPLLCOUNT.
Table 22-1. Clock Switching Timings (Worst Case)
Fro
m
Main Clock
SLCK
PLL Clock
To
Main
Clock
Clock
–
4 x SLCK +
2.5 x Main Clock
3 x PLL Clock +
4 x SLCK +
1 x Main Clock
SLCK
0.5 x Main Clock +
4.5 x SLCK
–
3 x PLL Clock +
5 x SLCK
PLL Clock
0.5 x Main Clock +
4 x SLCK +
PLLCOUNT x SLCK +
2.5 x PLLx Clock
2.5 x PLL Clock +
5 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
4 x SLCK +
PLLCOUNT x SLCK
Table 22-2. Clock Switching Timings between Two PLLs (Worst Case)
Fro
m
PLLA Clock
UPLL Clock
To
PLLA Clock
2.5 x PLLA Clock +
4 x SLCK +
PLLACOUNT x SLCK
3 x PLLA Clock +
4 x SLCK +
1.5 x PLLA Clock
UPLL
Clock
Clock
3 x UPLL Clock +
4 x SLCK +
1.5 x UPLL Clock
2.5 x UPLL Clock +
4 x SLCK +
UPLLCOUNT x SLCK