Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK データシート

642

SAM9G25 [DATASHEET]

11032D–ATARM–10-Mar-2014

The recommended error recovery procedure after a timeout is:



Issue the command completion signal disable if nIEN was cleared to zero and the RW_MULTIPLE_BLOCK 
(CMD61) response has been received.



Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response.



Issue a software reset to the CE-ATA device using FAST_IO (CMD39).

If STOP_TRANMISSION (CMD12) is successful, then the device is again ready for ATA commands. However, if the 
error recovery procedure does not work as expected or there is another timeout, the next step is to issue 
GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE (CMD0) is a hard reset to the device and completely resets 
all device states.

Note that after issuing GO_IDLE_STATE (CMD0), all device initialization needs to be completed again. If the CE-ATA 
device completes all MMC commands correctly but fails the ATA command with the ERR bit set in the ATA Status 
register, no error recovery action is required. The ATA command itself failed implying that the device could not complete 
the action requested, however, there was no communication or protocol failure. After the device signals an error by 
setting the ERR bit to one in the ATA Status register, the host may attempt to retry the command.

In boot operation mode, the processor can read boot data from the slave (MMC device) by keeping the CMD line low 
after power-on before issuing CMD1. The data can be read from either the boot area or user area, depending on register 
setting.

1.

Configure the HSMCI data bus width programming SDCBUS Field in the HSMCI_SDCR register. The 
BOOT_BUS_WIDTH field located in the device Extended CSD register must be set accordingly.

2.

Set the byte count to 512 bytes and the block count to the desired number of blocks, writing BLKLEN and BCNT 
fields of the HSMCI_BLKR Register.

3.

Issue the Boot Operation Request command by writing to the HSMCI_CMDR register with SPCMD field set to 
BOOTREQ, TRDIR set to READ and TRCMD set to “start data transfer”.

4.

The BOOT_ACK field located in the HSMCI_CMDR register must be set to one, if the BOOT_ACK field of the 
MMC device located in the Extended CSD register is set to one.

5.

Host processor can copy boot data sequentially as soon as the RXRDY flag is asserted.

6.

When Data transfer is completed, host processor shall terminate the boot stream by writing the HSMCI_CMDR 
register with SPCMD field set to BOOTEND.

1.

Configure the HSMCI data bus width by programming SDCBUS Field in the HSMCI_SDCR register. The 
BOOT_BUS_WIDTH field in the device Extended CSD register must be set accordingly.

2.

Set the byte count to 512 bytes and the block count to the desired number of blocks by writing BLKLEN and BCNT 
fields of the HSMCI_BLKR register.

3.

Enable DMA transfer in the HSMCI_DMA register.

4.

Configure DMA controller, program the total amount of data to be transferred and enable the relevant channel.

5.

Issue the Boot Operation Request command by writing to the HSMCI_CMDR register with SPCND set to 
BOOTREQ, TRDIR set to READ and TRCMD set to “start data transfer”.

6.

DMA controller copies the boot partition to the memory.

7.

When DMA transfer is completed, host processor shall terminate the boot stream by writing the HSMCI_CMDR 
register with SPCMD field set to BOOTEND.