Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK データシート
製品コード
AT91SAM9G25-EK
820
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
Figure 39-5. Elementary Time Unit (ETU)
39.7.2 Receiver and Transmitter Control
After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register
(US_CR). However, the receiver registers can be programmed before the receiver clock is enabled.
(US_CR). However, the receiver registers can be programmed before the receiver clock is enabled.
After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR).
However, the transmitter registers can be programmed before being enabled.
However, the transmitter registers can be programmed before being enabled.
The Receiver and the Transmitter can be enabled together or independently.
At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the
corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The software resets clear the
status flag and reset internal state machines but the user interface configuration registers hold the value configured prior
to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately
stopped.
corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The software resets clear the
status flag and reset internal state machines but the user interface configuration registers hold the value configured prior
to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately
stopped.
The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in
US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current
character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of
transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a
timeguard is programmed, it is handled normally.
US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current
character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of
transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a
timeguard is programmed, it is handled normally.
39.7.3 Synchronous and Asynchronous Modes
39.7.3.1 Transmitter Operations
The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1).
One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin
at each falling edge of the programmed serial clock.
One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin
at each falling edge of the programmed serial clock.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). Nine bits are
selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in
US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which
data bit is sent first. If written to 1, the most significant bit is sent first. If written to 0, the less significant bit is sent first. The
number of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode
only.
selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in
US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which
data bit is sent first. If written to 1, the most significant bit is sent first. If written to 0, the less significant bit is sent first. The
number of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode
only.
1 ETU
ISO7816 Clock
on SCK
ISO7816 I/O Line
on TXD
FI_DI_RATIO
ISO7816 Clock Cycles