Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK データシート

905

SAM9G25 [DATASHEET]

11032D–ATARM–10-Mar-2014

Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a 
conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable.

Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is 
provided by writing the Control Register (ADC_CR) with the START bit at 1. 

The hardware trigger can be selected by the TRGMOD field in the 

 between:



Any edge, either rising or falling or both, detected on the external trigger pin, TSADTRG. 



A continuous trigger, meaning the ADC Controller restarts the next sequence as soon as it finishes the current one



A periodic trigger, which is defined by programming the TRGPER field in the 

The minimum time between 2 consecutive trigger events must be strictly greater than the duration time of the longest 
conversion sequence according to configuration of registers ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2.

EOC0

GOVRE

CH0

(ADC_CHSR)

(ADC_SR)

(ADC_SR)

Trigger event

EOC1

CH1

(ADC_CHSR)

(ADC_SR)

OVRE0

(ADC_OVER)

Undefined Data

Data A

Data B

ADC_LCDR

Undefined Data

Data A

ADC_CDR0

Undefined Data

Data B

ADC_CDR1

Data C

Data C

Conversion C

Conversion A

DRDY

(ADC_SR)

Read ADC_CDR1

Read ADC_CDR0

Conversion B

Read ADC_OVER

Read ADC_SR

OVRE1

(ADC_OVER)