Infineon Technologies Door Module Power IC TLE 8201R DEMOBOARD TLE8201R DEMOBOARD TLE8201R データシート
製品コード
DEMOBOARD TLE8201R
TLE 8201R
Pin Configuration
Data Sheet Rev. 2.0
5
2006-06-07
2.2
Pin Definitions and Functions
Pin
Symbol
Function
cooling
tab
tab
GND
Cooling tab, internally connected to GND; to reduce thermal
resistance place cooling areas and thermal vias on PCB.
resistance place cooling areas and thermal vias on PCB.
1, 18,
19, 36
19, 36
GND
Ground; internally connected to cooling tab (heat slug).
2
OUT5
Power-Output of half-bridge 5; DMOS half-bridge
3
OUT6
Power-Output of half-bridge 6; DMOS half-bridge.
4, 15, 23,
26, 30, 33
26, 30, 33
Vs
Power supply; needs decoupling capacitors to GND. > 47µF
electrolytic in parallel with 100nF ceramic is recommended. All
Vs pins must be connected externally
electrolytic in parallel with 100nF ceramic is recommended. All
Vs pins must be connected externally
5
INH
Inhibit; active low. Sets the device in sleep mode with low
current consumption when left open or pulled to LOW. Has an
internal pull down current source
current consumption when left open or pulled to LOW. Has an
internal pull down current source
6
PWM1
Logic Input for direct power stage control; direct input to
control the high-side switches selected by the SPI xsel1 bits in
control register CtrlReg01
control the high-side switches selected by the SPI xsel1 bits in
control register CtrlReg01
7
PWM2
Logic Input for direct power stage control; direct input to
control the switches selected by the SPI xsel2 bits in control
register CtrlReg11
control the switches selected by the SPI xsel2 bits in control
register CtrlReg11
8
ISO
Current sense output; Mirrors the current of the high-side
switch selected by the current sense multiplexer control bits ISx
switch selected by the current sense multiplexer control bits ISx
9
Vcc
Logic Supply Voltage; needs decoupling capacitors to GND
(pin 1). 10µF electrolytic in parallel with 10nF ceramic is
recommended
(pin 1). 10µF electrolytic in parallel with 10nF ceramic is
recommended
10
DO
Serial Data Output; Transfers data to the master when the chip
is selected by CSN=LOW. Data transmission is synchronized by
CLK, DO state is changed on the rising edge of CLK. The most
significant bit (MSB) is transferred first. The pin is tristated as
long as CSN=HIGH
is selected by CSN=LOW. Data transmission is synchronized by
CLK, DO state is changed on the rising edge of CLK. The most
significant bit (MSB) is transferred first. The pin is tristated as
long as CSN=HIGH
11
CLK
Serial Data Clock Input; Receives the clock signal from the
master and clocks the SPI shift register. Has an internal pull
down current source
master and clocks the SPI shift register. Has an internal pull
down current source
12
CSN
Serial Port Chip Select Not Input; SPI communication is
enabled by pulling CSN to LOW. CLK must be LOW during the
transition of CSN. The CSN-pin has an internal pull-up current
source
enabled by pulling CSN to LOW. CLK must be LOW during the
transition of CSN. The CSN-pin has an internal pull-up current
source