Atmel Evaluation Kit for ATxmega32E5, 8/16-bit AVR XMEGA Microcontroller Atmel ATXMEGAE5-XPLD ATXMEGAE5-XPLD データシート
製品コード
ATXMEGAE5-XPLD
15
XMEGA E5 [DATASHEET]
Atmel-8153H–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–07/2014
8.11
I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the
I/O register related to the clock system, the event system, and the waveform extensions. As long as the lock is enabled,
all related I/O registers are locked and they cannot be written from the application software. The lock registers
themselves are protected by the configuration change protection mechanism.
I/O register related to the clock system, the event system, and the waveform extensions. As long as the lock is enabled,
all related I/O registers are locked and they cannot be written from the application software. The lock registers
themselves are protected by the configuration change protection mechanism.
8.12
Flash and EEPROM Page Size
The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the
flash and byte accessible for the EEPROM.
flash and byte accessible for the EEPROM.
shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and erase
operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash access the
Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page number and the
least significant address bits (FWORD) give the word in the page.
Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page number and the
least significant address bits (FWORD) give the word in the page.
Table 8-2.
Number of words and pages in the flash.
shows EEPROM memory organization for the Atmel AVR XMEGA E5 devices. EEPROM write and erase
operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For
EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in the address
(E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page.
EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in the address
(E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page.
Table 8-3.
Number of words and pages in the EEPROM.
Devices
PC size
Flash size
Page Size
FWORD
FPAGE
Application
Boot
bits
bytes
words
Size
No of
pages
pages
Size
No of
pages
pages
ATxmega32E5
15
32K+4K
64
Z[6:0]
Z[14:7]
32K
256
4K
32
ATxmega16E5
14
16K+4K
64
Z[6:0]
Z[13:7]
16K
128
4K
32
ATxmega8E5
13
8K+2K
64
Z[6:0]
Z[12:7]
8K
64
2K
16
Devices
EEPROM
Page Size
E2BYTE
E2PAGE
No of Pages
Size
bytes
ATxmega32E5
1K
32
ADDR[4:0]
ADDR[10:5]
32
ATxmega16E5
512Bytes
32
ADDR[4:0]
ADDR[10:5]
16
ATxmega8E5
512Bytes
32
ADDR[4:0]
ADDR[10:5]
16