Atmel Evaluation Kit for ATxmega32E5, 8/16-bit AVR XMEGA Microcontroller Atmel ATXMEGAE5-XPLD ATXMEGAE5-XPLD データシート
製品コード
ATXMEGAE5-XPLD
44
XMEGA E5 [DATASHEET]
Atmel-8153H–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–07/2014
23.
SPI – Serial Peripheral Interface
23.1
Features
z
One SPI peripheral
z
Full-duplex, three-wire synchronous data transfer
z
Master or slave operation
z
Lsb first or msb first data transfer
z
Eight programmable bit rates
z
Interrupt flag at the end of transmission
z
Write collision flag to indicate data collision
z
Wake up from idle sleep mode
z
Double speed master mode
23.2
Overview
The Serial Peripheral Interface (SPI) is a high-speed, full duplex, synchronous data transfer interface using three or four
pins. It allows fast communication between an AVR XMEGA device and peripheral devices or between several
microcontrollers.
pins. It allows fast communication between an AVR XMEGA device and peripheral devices or between several
microcontrollers.
A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions. The
interconnection between master and slave devices with SPI is shown in
interconnection between master and slave devices with SPI is shown in
. The system consists of two shift
registers and a clock generator. The SPI master initiates the communication by pulling the slave select (SS) signal low
for the desired slave. Master and slave prepare the data to be sent in their respective shift registers, and the master
generates the required clock pulses on the SCK line to interchange data. Data are always shifted from master to slave on
the master output, slave input (MOSI) line, and from slave to master on the master input, slave output (MISO) line. After
each data packet, the master can synchronize the slave by pulling the SS line high.
for the desired slave. Master and slave prepare the data to be sent in their respective shift registers, and the master
generates the required clock pulses on the SCK line to interchange data. Data are always shifted from master to slave on
the master output, slave input (MOSI) line, and from slave to master on the master input, slave output (MISO) line. After
each data packet, the master can synchronize the slave by pulling the SS line high.
Figure 23-1. SPI master-slave interconnection
By default, the SPI module is single buffered and transmit direction and double buffered in the receive direction. A byte
written to the transmit data register will be copied to the shift register when a full character has been received. When
receiving data, a received character must be read from the transmit data register before the third character has been
completely shifted in to avoid losing data. Optionally, buffer modes can be enabled. When used, one buffer is available
for transmitter and a double buffer for reception.
written to the transmit data register will be copied to the shift register when a full character has been received. When
receiving data, a received character must be read from the transmit data register before the third character has been
completely shifted in to avoid losing data. Optionally, buffer modes can be enabled. When used, one buffer is available
for transmitter and a double buffer for reception.
PORTC has one SPI. Notation of this is SPIC
8-bit Shift Register
msb
Transmit Data Register
(DATA)
Receive Buffer Register
Receive Data Register
(DATA)
MOSI
lsb
MISO
SCK
SS
SLAVE
8-bit Shift Register
msb
Transmit Data Register
(DATA)
Receive Buffer Register
Receive Data Register
(DATA)
MOSI
lsb
MISO
SCK
SS
MASTER
SPI CLOCK
GENERATOR