Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD データシート

製品コード

ATSAM4S-XPLD

644

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

Figure 33-19.TWI Read Operation with Single Data Byte and Internal Address

Set the Control register:

- Master enable

TWI_CR = MSEN + SVDIS

Set the Master Mode register:

- Device slave address

- Internal address size (IADRSZ)

- Transfer direction bit

Read ==> bit MREAD = 1

Read Status register

TXCOMP = 1

END

BEGIN

Yes

Set TWI clock

(CLDIV, CHDIV, CKDIV) in TWI_CWGR

(Needed only once)

Yes

Set the internal address

TWI_IADR = address

Start the transfer

TWI_CR = START STOP

Read Status register

RXRDY = 1

Read Receive Holding register