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Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD データシート

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ATSAM4S-WPIR-RD
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SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
106
Pre-indexed Addressing
 
The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the 
address for the memory access and written back into the register Rn. The assembly language syntax for this mode 
is:
[Rn, #offset]!
Post-indexed Addressing
 
The address obtained from the register Rn is used as the address for the memory access. The offset value is 
added to or subtracted from the address, and written back into the register Rn. The assembly language syntax for 
this mode is:
[Rn], #offset
The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed 
or unsigned. See 
The table below shows the ranges of offset for immediate, pre-indexed and post-indexed forms.
Restrictions
For load instructions:
Rt
 can be SP or PC for word loads only
Rt
 must be different from Rt2 for two-word loads
Rn
 must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
When Rt is PC in a word load instruction:
Bit[0] of the loaded value must be 1 for correct execution
A branch occurs to the address created by changing bit[0] of the loaded value to 0
If the instruction is conditional, it must be the last instruction in the IT block.
For store instructions:
Rt
 can be SP for word stores only
Rt
 must not be PC
Rn
 must not be PC
Rn
 must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
Condition Flags
These instructions do not change the flags.
Table 12-18.
Offset Ranges
Instruction Type
Immediate Offset
Pre-indexed
Post-indexed
Word, halfword, signed 
halfword, byte, or signed byte
-255 to 4095
-255 to 255
-255 to 255
Two words
multiple of 4 in the 
range -1020 to 1020
multiple of 4 in the 
range -1020 to 1020
multiple of 4 in the 
range -1020 to 1020