Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD データシート
製品コード
ATSAM4S-WPIR-RD
1089
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
42.7.12 ADC Interrupt Status Register
Name:
ADC_ISR
Address:
0x40038030
Access:
Read-only
• EOCx: End of Conversion x
0: The corresponding analog channel is disabled, or the conversion is not finished. This flag is cleared when reading the
corresponding ADC_CDRx registers.
1: The corresponding analog channel is enabled and conversion is complete.
1: The corresponding analog channel is enabled and conversion is complete.
• EOCAL: End of Calibration Sequence
0: Calibration sequence is ongoing, or no calibration sequence has been requested.
1: Calibration sequence is complete.
1: Calibration sequence is complete.
• DRDY: Data Ready
0: No data has been converted since the last read of ADC_LCDR.
1: At least one data has been converted and is available in ADC_LCDR.
1: At least one data has been converted and is available in ADC_LCDR.
• GOVRE: General Overrun Error
0: No General Overrun Error occurred since the last read of ADC_ISR.
1: At least one General Overrun Error has occurred since the last read of ADC_ISR.
1: At least one General Overrun Error has occurred since the last read of ADC_ISR.
• COMPE: Comparison Error
0: No Comparison Error since the last read of ADC_ISR.
1: At least one Comparison Error (defined in the ADC_EMR and ADC_CWR) has occurred since the last read of ADC_ISR.
1: At least one Comparison Error (defined in the ADC_EMR and ADC_CWR) has occurred since the last read of ADC_ISR.
• ENDRX: End of Receiver Transfer
0: The end of transfer signal from the receive PDC channel is inactive.
1: The end of transfer signal from the receive PDC channel is active.
1: The end of transfer signal from the receive PDC channel is active.
• RXBUFF: Reception Buffer Full
0: The signal Buffer Full from the Receive PDC channel is inactive.
1: The signal Buffer Full from the Receive PDC channel is active.
1: The signal Buffer Full from the Receive PDC channel is active.
31
30
29
28
27
26
25
24
–
–
–
RXBUFF
ENDRX
COMPE
GOVRE
DRDY
23
22
21
20
19
18
17
16
EOCAL
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
EOC15
EOC14
EOC13
EOC12
EOC11
EOC10
EOC9
EOC8
7
6
5
4
3
2
1
0
EOC7
EOC6
EOC5
EOC4
EOC3
EOC2
EOC1
EOC0