Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD データシート
製品コード
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
854
• LDBSTOP: Counter Clock Stopped with RB Loading
0: Counter clock is not stopped when RB loading occurs.
1: Counter clock is stopped when RB loading occurs.
1: Counter clock is stopped when RB loading occurs.
• LDBDIS: Counter Clock Disable with RB Loading
0: Counter clock is not disabled when RB loading occurs.
1: Counter clock is disabled when RB loading occurs.
1: Counter clock is disabled when RB loading occurs.
• ETRGEDG: External Trigger Edge Selection
• ABETRG: TIOA or TIOB External Trigger Selection
0: TIOB is used as an external trigger.
1: TIOA is used as an external trigger.
1: TIOA is used as an external trigger.
• CPCTRG: RC Compare Trigger Enable
0: RC Compare has no effect on the counter and its clock.
1: RC Compare resets the counter and starts the counter clock.
1: RC Compare resets the counter and starts the counter clock.
• WAVE: Waveform Mode
0: Capture Mode is enabled.
1: Capture Mode is disabled (Waveform Mode is enabled).
1: Capture Mode is disabled (Waveform Mode is enabled).
• LDRA: RA Loading Edge Selection
• LDRB: RB Loading Edge Selection
Value
Name
Description
0
NONE
The clock is not gated by an external signal.
1
RISING
Rising edge
2
FALLING
Falling edge
3
EDGE
Each edge
Value
Name
Description
0
NONE
None
1
RISING
Rising edge of TIOA
2
FALLING
Falling edge of TIOA
3
EDGE
Each edge of TIOA
Value
Name
Description
0
NONE
None
1
RISING
Rising edge of TIOA
2
FALLING
Falling edge of TIOA
3
EDGE
Each edge of TIOA