Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート
製品コード
AT32UC3A3-XPLD
172
32072H–AVR32–10/2012
AT32UC3A3
14.6.5.5
Application example
illustrates an example of a CompactFlash application. CFCS0 and
CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direc-
tion and the output enable of the buffers between the EBI and the CompactFlash Device. The
timing of the CFCS0 signal is identical to the NCS[4] signal. The CFRNW signal remains valid
throughout the transfer, as does the address bus. The CompactFlash _WAIT signal is con-
nected to the NWAIT input of the Static Memory Controller. For details on these waveforms and
timings, refer to the SMC Section.
tion and the output enable of the buffers between the EBI and the CompactFlash Device. The
timing of the CFCS0 signal is identical to the NCS[4] signal. The CFRNW signal remains valid
throughout the transfer, as does the address bus. The CompactFlash _WAIT signal is con-
nected to the NWAIT input of the Static Memory Controller. For details on these waveforms and
timings, refer to the SMC Section.
Figure 14-4. CompactFlash Application Example with I/O mode
Table 14-8.
Shared CompactFlash Interface Multiplexing
Pins
Access to
CompactFlash Device
CompactFlash Device
CompactFlash Signals
NRD
CFNOE
NWE0
CFNWE
NWE1
CFNIORD
CFRNW
CFRNW
EBI
CompactFlash
Connector
DATA[15:0]
CFRNW
NCS[4]
Pxx
ADDR[10:0]
ADDR[22]
NRD
NWE0
NWE1
CFCE1
CFCE2
NWAIT
_WAIT
_CE2
_CE1
_IOWR
_IORD
_WE
_OE
_REG
A[10:0]
_CD2
_CD1
D[15:0]
/OE
/OE
DIR
ADDR[21]