Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート
製品コード
AT32UC3A3-XPLD
191
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-13. WRITEMODE = 1. The Write Operation Is Controlled by NWE
•Write is controlled by NCS (MODE.WRITEMODE = 0)
shows the waveforms of a write operation with MODE.WRITEMODE
written to zero. The data is put on the bus during the pulse and hold steps of the NCS signal.
The internal data buffers are turned out after the NCSWRSETUP time, and until the end of the
write cycle, regardless of the programmed waveform on NWE.
The internal data buffers are turned out after the NCSWRSETUP time, and until the end of the
write cycle, regardless of the programmed waveform on NWE.
Figure 15-14. WRITEMODE = 0. The Write Operation Is Controlled by NCS
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE,
NWR0, NWR1
NCS
D[15:0]
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE,
NWR0, NWR1
NCS
D[15:0]