Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート
製品コード
AT32UC3A3-XPLD
220
32072H–AVR32–10/2012
AT32UC3A3
16.3
Block Diagram
Figure 16-1. SDRAM Controller Block Diagram
16.4
I/O Lines Description
M em ory
C ontroller
P ow er
M anager
C LK _S D R A M C
S D R A M C
C hip S elect
S D R A M C
Interrupt
S D R A M C
U ser Interface
P eripheral B us
I/O
C ontroller
S D C S
S D C K
S D C K E
B A[1:0]
R A S
C A S
S D W E
D Q M [0]
S D R A M C _A [9:0]
D [15:0]
E B I
M U X Logic
D A TA [15:0]
S D C K
S D C K E
N C S [1]
R A S
C A S
A D D R [17:16]
S D W E
A D D R[0]
D Q M [1]
N W E 1
A D D R [11:2]
S D R A M C _A [10]
S D A10
S D R A M C _A [12:11]
A D D R [13:14]
Table 16-1.
I/O Lines Description
Name
Description
Type
Active Level
SDCK
SDRAM Clock
Output
SDCKE
SDRAM Clock Enable
Output
High
SDCS
SDRAM Chip Select
Output
Low
BA[1:0]
Bank Select Signals
Output
RAS
Row Signal
Output
Low
CAS
Column Signal
Output
Low
SDWE
SDRAM Write Enable
Output
Low