Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

32072H–AVR32–10/2012

bit in the Interrupt Status Register (ISR.TERR) will be set and the DMA channel that caused the
error will be stopped. In order to restart the channel, the user must program the Memory
Address Register to a valid address and then write a one to the Error Clear bit in the Control
Register (CR.ECLR). If the Transfer Error interrupt is enabled, an interrupt request will be gener-
ated when a transfer error occurs.

Up to two performance monitors allow the user to measure the activity and stall cycles for PDCA
transfers. To monitor a PDCA channel, the corresponding channel number must be written to
one of the MON0/1CH fields in the Performance Control Register (PCONTROL) and a one must
be written to the corresponding CH0/1EN bit in the same register. 

Due to performance monitor hardware resource sharing, the two monitor channels should NOT
be programmed to monitor the same PDCA channel. This may result in UNDEFINED perfor-
mance monitor behavior.

Three different parameters can be measured by each channel:

• The number of data transfer cycles since last channel reset, both for read and write

• The number of stall cycles since last channel reset, both for read and write

• The maximum latency since last channel reset, both for read and write

These measurements can be extracted by software and used to generate indicators for bus
latency, bus load, and maximum bus latency.

Each of the counters has a fixed width, and may therefore overflow. When an overflow is
encountered in either the Performance Channel Data Read/Write Cycle registers (PRDATA0/1
and PWDATA0/1) or the Performance Channel Read/Write Stall Cycles registers (PRSTALL0/1
and PWSTALL0/1) of a channel, all registers in the channel are reset. This behavior is altered if
the Channel Overflow Freeze bit is one in the Performance Control register (PCON-
TROL.CH0/1OVF). If this bit is one, the channel registers are frozen when either DATA or
STALL reaches its maximum value. This simplifies one-shot readout of the counter values.

The registers can also be manually reset by writing a one to the Channel Reset bit in the PCON-
TROL register (PCONTROL.CH0/1RES). The Performance Channel Read/Write Latency
registers (PRLAT0/1 and PWLAT0/1) are saturating when their maximum count value is
reached. The PRLAT0/1 and PWLAT0/1 registers can only be reset by writing a one to the cor-
responding reset bit in PCONTROL (PCONTROL.CH0/1RES).

A counter is enabled by writing a one to the Channel Enable bit in the Performance Control Reg-
ister (PCONTROL.CH0/1EN).