Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

32072H–AVR32–10/2012

Software selects between the hardware or software handshaking interface on a per-channel
basis. Software handshaking is accomplished through memory-mapped registers, while hard-
ware handshaking is accomplished using a dedicated handshaking interface.

When the slave peripheral requires the DMACA to perform a DMA transaction, it communicates
this request by sending an interrupt to the CPU or interrupt controller.

The interrupt service routine then uses the software registers to initiate and control a DMA trans-
action. These software registers are used to implement the software handshaking interface.

The HS_SEL_SRC/HS_SEL_DST

 

bit in the CFGx channel configuration register must be set to

enable software handshaking. 

When the peripheral is not the flow controller, then the last transaction registers LstSrcReg and
LstDstReg

 

are not used, and the values in these registers are ignored.

Writing a 1 to the ReqSrcReg[x]/ReqDstReg[x] register is always interpreted as a burst transac-
tion request, where x is the channel number. However, in order for a burst transaction request to
start, software must write a 1 to the SglReqSrcReg[x]/SglReqDstReg[x] register.

You can write a 1 to the SglReqSrcReg[x]/SglReqDstReg[x] and ReqSrcReg[x]/ReqDstReg[x]
registers in any order, but both registers must be asserted in order to initiate a burst transaction.
Upon completion of the burst transaction, the hardware clears the SglReqSrcReg[x]/SglReqD-
stReg[x] and ReqSrcReg[x]/ReqDstReg[x] registers.

Writing a 1 to the SglReqSrcReg/SglReqDstReg

 

initiates a single transaction. Upon completion

of the single transaction, both the SglReqSrcReg/SglReqDstReg and ReqSrcReg/ReqDstReg
bits are cleared by hardware. Therefore, writing a 1 to the ReqSrcReg/ReqDstReg is ignored
while a single transaction has been initiated, and the requested burst transaction is not serviced. 

Again, writing a 1 to the ReqSrcReg/ReqDstReg register is always a burst transaction request.
However, in order for a burst transaction request to start, the corresponding channel bit in the
SglReqSrcReg/SglReqDstReg must be asserted. Therefore, to ensure that a burst transaction is
serviced, you must write a 1 to the ReqSrcReg/ReqDstReg before writing a 1 to the SglReqSr-
cReg/SglReqDstReg register. 

Software can poll the relevant channel bit in the SglReqSrcReg/ SglReqDstReg and ReqSr-
cReg/ReqDstReg registers. When both are 0, then either the requested burst or single
transaction has completed. Alternatively, the IntSrcTran or IntDstTran interrupts can be enabled
and unmasked in order to generate an interrupt when the requested source or destination trans-
action has completed.

Note:

The transaction-complete interrupts are triggered when both single and burst transactions are 
complete. The same transaction-complete interrupt is used for both single and burst transactions.

There are 

8

 hardware handshaking interfaces between the DMACA and peripherals. Refer to

the module configuration chapter for the device-specific mapping of these interfaces.