Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

32072H–AVR32–10/2012

Figure 20-2. Overview of the GPIO Pad Connections

When a pin is multiplexed with one or more peripheral functions, the selection is controlled with
the GPIO Enable Register (GPER). If a bit in GPER is written to one, the corresponding pin is
controlled by the GPIO. If a bit is written to zero, the corresponding pin is controlled by a periph-
eral function.

The GPIO provides multiplexing of up to four peripheral functions on a single pin. The selection
is performed by accessing Peripheral Mux Register 0 (PMR0) and Peripheral Mux Register 1
(PMR1). 

When the I/O line is assigned to a peripheral function, i.e. the corresponding bit in GPER is writ-
ten to zero, the drive of the I/O line is controlled by the peripheral. The peripheral, depending on
the value in PMR0 and PMR1, determines whether the pin is driven or not.

When the I/O line is controlled by the GPIO, the value of the Output Driver Enable Register
(ODER) determines if the pin is driven or not. When a bit in this register is written to one, the cor-

0

1

GPER

1

0

OVR

ODER

PMR1

Periph. A output enable

Periph. B output enable

Periph. C output enable

Periph. D output enable

Periph. A output data

Periph. B output data

Periph. C output data

Periph. D output data

PAD

PUER

Periph. A input data

Periph. B input data

Periph. C input data

Periph. D input data

PVR

0

1

Glitch Filter

GFER

Edge Detector

1

0

Interrupt Request

IMR1

PMR0

IMR0

IER