Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

32072H–AVR32–10/2012

TTOUT: Prescaled clock cycles used to time SMBUS timeout T

TIMEOUT

.

SUDAT: Non-prescaled clock cycles for data setup and hold count. Used to time T

SU_DAT

.

EXP: Specifies the clock prescaler setting used for the SMBUS timeouts.

Figure 22-6. Bus Timing Diagram

Operation of the TWIS is mainly controlled by the Control Register (CR). The following list pres-
ents the main steps in a typical communication:

4.

Before any transfers can be performed, bus timings must be configured by writing to the 
Timing Register (TR).If the Peripheral DMA Controller is to be used for the transfers, it 
must be set up.

5.

The Control Register (CR) must be configured with information such as the slave 
address, SMBus mode, Packet Error Checking (PEC), number of bytes to transfer, and 
which addresses to match.

The interrupt system can be set up to generate interrupt request on specific events or error con-
ditions, for example when a byte has been received.

The NBYTES register is only used in SMBus mode, when PEC is enabled. In I²C mode or in
SMBus mode when PEC is disabled, the NBYTES register is not used, and should be written to
zero. NBYTES is updated by hardware, so in order to avoid hazards, software updates of
NBYTES can only be done through writes to the NBYTES register.

The TWIS can be set up to match several different addresses. More than one address match
may be enabled simultaneously, allowing the TWIS to be assigned to several addresses. The
address matching phase is initiated after a START or REPEATED START condition. When the
TWIS receives an address that generates an address match, an ACK is automatically returned
to the master.

S

t

HD:STA

t LOW

t

SU:DAT

t HIGH

t

HD:DAT

t LOW

P

t

SU:STO

Sr

t

SU:STA

t

SU:DAT