Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

32072H–AVR32–10/2012

This chapter lists the different bus events, and how they affect bits in the TWIM registers. This is
intended to help writing drivers for the TWIM.

Bus Events

Master transmitter has sent 
a data byte

SR.THR is cleared.

Master receiver has 
received a data byte

SR.RHR is set.

Start+Sadr sent, no ack 
received from slave

SR.ANAK is set.

SR.CCOMP not set.

CMDR.VALID remains set.

STOP automatically transmitted on bus.

Data byte sent to slave, no 
ack received from slave

SR.DNAK is set.

SR.CCOMP not set.

CMDR.VALID remains set.

STOP automatically transmitted on bus.

Arbitration lost

SR.ARBLST is set.

SR.CCOMP not set.

CMDR.VALID remains set.

TWCK and TWD immediately released to a pulled-up state.

SMBus Alert received

SR.SMBALERT is set.

SMBus timeout received

SR.SMBTOUT is set.

SR.CCOMP not set.

CMDR.VALID remains set.

STOP automatically transmitted on bus.

Master transmitter receives 
SMBus PEC Error

SR.DNAK is set.

SR.CCOMP not set.

CMDR.VALID remains set.

STOP automatically transmitted on bus.

Master receiver discovers 
SMBus PEC Error

SR.PECERR is set.

SR.CCOMP not set.

CMDR.VALID remains set.

STOP automatically transmitted on bus.

CR.STOP is written by user

SR.STOP is set.

SR.CCOMP set.

CMDR.VALID remains set.

STOP transmitted on bus after current byte transfer has finished.