Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

32072H–AVR32–10/2012

Figure 24-4. Divided Clock Block Diagram 

The peripheral clock divider is determined by the 12-bit Clock Divider field (its maximal value is
4095) in the Clock Mode Register (CMR.DIV), allowing a peripheral clock division by up to 8190.
The divided clock is provided to both the receiver and transmitter. When this field is written to
zero, the clock divider is not used and remains inactive.

When CMR.DIV is written to a value equal to or greater than one, the divided clock has a fre-
quency of CLK_SSC divided by two times CMR.DIV. Each level of the divided clock has a
duration of the peripheral clock multiplied by CMR.DIV. This ensures a 50% duty cycle for the
divided clock regardless of whether the CMR.DIV value is even or odd.

Figure 24-5.  Divided Clock Generation 

The transmitter clock is generated from the receiver clock, the divider clock, or an external clock
scanned on the TX_CLOCK pin. The transmitter clock is selected by writing to the Transmit
Clock Selection field in the Transmit Clock Mode Register (TCMR.CKS). The transmit clock can

Range of Clock Divider

CLK_SSC / 2

CLK_SSC / 8190

CMR

/ 2

CLK_SSC

Divided Clock

12-bit Counter

Clock Divider

CLK_SSC

Divided Clock

DIV = 1

CLK_SSC

Divided Clock

DIV = 3

Divided Clock Frequency = CLK_SSC/2

Divided Clock Frequency = CLK_SSC/6