Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート
製品コード
AT32UC3A3-XPLD
541
32072H–AVR32–10/2012
AT32UC3A3
24.9.13
Status Register
Name:
SR
Access Type:
Read-only
Offset:
0x40
Reset value:
0x000000CC
• RXEN: Receive Enable
This bit is set when the CR.RXEN bit is written to one.
This bit is cleared when no data are being processed and the CR.RXDIS bit has been written to one.
• TXEN: Transmit Enable
This bit is set when the CR.TXEN bit is written to one.
This bit is cleared when no data are being processed and the CR.TXDIS bit has been written to one.
• RXSYN: Receive Sync
This bit is set when a Receive Sync has occurred.
This bit is cleared when the SR register is read.
• TXSYN: Transmit Sync
This bit is set when a Transmit Sync has occurred.
This bit is cleared when the SR register is read.
• CP1: Compare 1
This bit is set when compare 1 has occurred.
This bit is cleared when the SR register is read.
• CP0: Compare 0
This bit is set when compare 0 has occurred.
This bit is cleared when the SR register is read.
• OVRUN: Receive Overrun
This bit is set when data has been loaded in the RHR register while previous data has not yet been read.
This bit is cleared when the SR register is read.
• RXRDY: Receive Ready
This bit is set when data has been received and loaded in the RHR register.
This bit is cleared when the RHR register is empty.
• TXEMPTY: Transmit Empty
This bit is set when the last data written in the THR register has been loaded in the TSR register and last data loaded in the TSR
register has been transmitted.
This bit is cleared when data remains in the THR register or is currently transmitted from the TSR register.
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
-
RXEN
TXEN
15
14
13
12
11
10
9
8
-
-
-
-
RXSYN
TXSYN
CP1
CP0
7
6
5
4
3
2
1
0
-
-
OVRUN
RXRDY
-
-
TXEMPTY
TXRDY