Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

32072H–AVR32–10/2012

Figure 25-28. Header Reception

See also 

. 

Synchronization is only done by the slave. If the Sync byte is not 0x55, an Inconsistent Sync
Field error is generated, and the LIN Inconsistend Sync Field Error bit in CSR (CSR.LINISFE) is
set. An interrupt request is generated if the LINISFE bit in IMR is set. CSR.LINISFE is cleared by
writing a one to CR.RSTSTA. The time between falling edges is measured by a 19-bit counter,
driven by the sampling clock (see 

).

Figure 25-29. Sync Field

The counter starts when the Sync field start bit is detected, and continues for eight bit periods.
The 16 most significant bits (counter value divided by 8) becomes the new clock divider
(BRGR.CD), and the three least significant bits (the remainder) becomes the new fractional part
(BRGR.FP).

Figure 25-30. Slave Node Synchronization

The synchronization accuracy depends on:

Break Field

13 dominant bits (at 0)

Break

Delimiter

1 recessive bit

(at 1)

Start

Bit

1

0

1

0

1

0

1

0

Stop

Bit

Start

Bit

ID0 ID1 ID2

ID4

ID3

ID6

ID5

ID7

Stop

Bit

Synch Byte = 0x55

Baud Rate

Clock

RXD

Write US_CR

With RSTSTA=1

US_LINIR

LINID

Start

bit

Stop

bit

Synch Field

8 Tbit

2 Tbit

2 Tbit

2 Tbit

2 Tbit

RXD

Baud Rate

 Clock

LINIDRX

Synchro Counter

000_0011_0001_0110_1101

BRGR

Clcok Divider (CD)

0000_0110_0010_1101

BRGR

Fractional Part (FP)

101

Initial CD

Initial FP

Reset

Start

Bit

1

0

1

0

1

0

1

0

Stop

Bit

Start

Bit

ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7

Break Field

13 dominant bits (at 0)

Stop

Bit

Break

Delimiter

1 recessive bit

(at 1)

Synch Byte = 0x55