Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

32072H–AVR32–10/2012

After a hardware reset, the USBB is disabled. When enabled, the USBB runs either in device
mode or in host mode according to the ID detection.

If the USB_ID pin is not connected to ground, the USB_ID Pin State bit in the General Status
register (USBSTA.ID) is set (the internal pull-up resistor of the USB_ID pin must be enabled by
the I/O Controller) and device mode is engaged.

The USBSTA.ID bit is cleared when a low level has been detected on the USB_ID pin. Host
mode is then engaged.

 describes the USBB main states.

Figure 27-5. General States

After a hardware reset, the USBB is in the Reset state. In this state:

• The macro is disabled. The USBB Enable bit in the General Control register 

(USBCON.USBE) is zero.

• The macro clock is stopped in order to minimize power consumption. The Freeze USB Clock 

bit in USBCON (USBON.FRZCLK) is set.

• The UTMI is in suspend mode.

• The internal states and registers of the device and host modes are reset.

• The DPRAM is not cleared and is accessible.

• The USBSTA.ID bit and the VBus Level bit in the UBSTA (UBSTA.VBUS) reflect the states of 

the USB_ID and USB_VBUS input pins.

• The OTG Pad Enable (OTGPADE) bit, the VBus Polarity (VBUSPO) bit, the FRZCLK bit, the 

USBE bit, the USB_ID Pin Enable (UIDE) bit, the USBB Mode (UIMOD) bit in USBCON, and 
the Low-Speed Mode Force bit in the Device General Control (UDCON.LS) register can be 
written by software, so that the user can program pads and speed before enabling the macro, 
but their value is only taken into account once the macro is enabled and unfrozen.

Device

Reset

USBE = 0

<any

other

state>

USBE = 1

ID = 1

Macro off:
USBE = 0

Clock stopped:

FRZCLK = 1

USBE = 0

Host

USBE = 0

   HW

RESET

USBE = 1

ID = 0