Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

製品コード
AT32UC3A3-XPLD
ページ / 1021
706
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.14
Endpoint n Control Register 
Register Name:
UECONn, n in [0..7]
Access Type:
Read-Only
Offset:
0x01C0 + (n * 0x04)
Reset Value:
0x00000000
• STALLRQ: STALL Request
This bit is set when the STALLRQS bit is written to one. This will request to send a STALL handshake to the host.
This bit is cleared when a new SETUP packet is received or when the STALLRQC bit is written to zero.
• RSTDT: Reset Data Toggle
This bit is set when the RSTDTS bit is written to one. This will clear the data toggle sequence, i.e., set to Data0 the data toggle 
sequence of the next sent (IN endpoints) or received (OUT endpoints) packet.
This bit is cleared instantaneously.
The user does not have to wait for this bit to be cleared.
• NYETDIS: NYET token disable
This bit is set when the NYETDISS bit is written to one. This will send a ACK handshake instead of a NYET handshake in high-
speed mode.
This bit is cleared when the NYETDISC bit is written to one.This will let the USBB handling the high-speed handshake following 
the usb 2.0 standard.
• EPDISHDMA: Endpoint Interrupts Disable HDMA Request Enable
This bit is set when the EPDISHDMAS is written to one. This will pause the on-going DMA channel n transfer on any Endpoint n 
interrupt (EPnINT), whatever the state of the Endpoint n Interrupt Enable bit (EPnINTE).
The user then has to acknowledge or to disable the interrupt source (e.g. RXOUTI) or to clear the EPDISHDMA bit (by writing a 
one to the EPDISHDMAC bit) in order to complete the DMA transfer.
In ping-pong mode, if the interrupt is associated to a new system-bank packet (e.g. Bank1) and the current DMA transfer is 
running on the previous packet (Bank0), then the previous-packet DMA transfer completes normally, but the new-packet DMA 
transfer will not start (not requested).
If the interrupt is not associated to a new system-bank packet (NAKINI, NAKOUTI, etc.), then the request cancellation may 
occur at any time and may immediately pause the current DMA transfer.
This may be used for example to identify erroneous packets, to prevent them from being transferred into a buffer, to complete a 
DMA transfer by software after reception of a short packet, etc.
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
STALLRQ
RSTDT
NYETDIS
EPDISHDMA
15
14
13
12
11
10
9
8
-
FIFOCON
KILLBK
NBUSYBKE
-
ERRORTRANSE
DATAXE
MDATAE
7
6
5
4
3
2
1
0
SHORT
PACKETE
STALLEDE/
CRCERRE
OVERFE
NAKINE/ 
HBISOFLUSHE
NAKOUTE/ 
HBISOINERRE
RXSTPE/
UNDERFE
RXOUTE
TXINE