Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

32072H–AVR32–10/2012

UHINT

Read-Only

0x0404

0x00000000

This bit is set when an interrupt is triggered by the DMA channel n. This triggers a USB interrupt if the corresponding 

DMAnINTE is one (UHINTE register).

This bit is cleared when the UHDMAnSTATUS interrupt source is cleared.

This bit is set when an interrupt is triggered by the endpoint n (UPSTAn). This triggers a USB interrupt if the corresponding pipe 

interrupt enable bit is one (UHINTE register). 

This bit is cleared when the interrupt source is served. 

This bit is set when the host controller is in the suspend mode (SOFE is zero) and an upstream resume from the peripheral is 

detected.

This bit is set when the host controller is in the suspend mode (SOFE is zero) and a peripheral disconnection is detected.

This bit is set when the host controller is in the Idle state (USBSTA.VBUSRQ is zero, no VBus is generated).

This interrupt is generated even if the clock is frozen by the FRZCLK bit.

This bit is set when a SOF is issued by the Host controller. This triggers a USB interrupt when HSOFE is one. When using the 

host controller in low speed mode, this bit is also set when a keep-alive is sent.

This bit is cleared when the HSOFIC bit is written to one.

This bit is set when an Upstream Resume has been received from the Device.

This bit is cleared when the RXRSMIC is written to one.

This bit set when a Downstream Resume has been sent to the Device.

This bit is cleared when the RSMEDIC bit is written to one.

This bit is set when a USB Reset has been sent to the device.

This bit is cleared when the RSTIC bit is written to one.

31

30

29

28

27

26

25

24

DMA7INT

DMA6INT

DMA5INT

DMA4INT

DMA3INT

DMA2INT

DMA1INT

-

23

22

21

20

19

18

17

16

-

-

-

-

-

-

-

15

14

13

12

11

10

9

8

P7INT

P6INT

P5INT

P4INT

P3INT

P2INT

P1INT

P0INT

7

6

5

4

3

2

1

0

-

HWUPI

HSOFI

RXRSMI

RSMEDI

RSTI

DDISCI

DCONNI